Battery-powered portable electronic devices such as laptop computers, cell phones and personal digital assistants have become increasingly common of late. One major limitation of these devices is the amount of power they consume, which results in a fairly short operating life on a set of disposable batteries or on a single charge of a rechargeable battery. Although battery technology has improved recently, the most direct way to increase the amount of time that these devices can run on their batteries is to reduce the amount of power the devices consume.
Every portable electronic device has at least some semiconductor memory. Typically these devices have two types of semiconductor random access memory (RAM): static RAM (SRAM), which retains its contents as long as power is supplied; and dynamic RAM (DRAM), which loses its contents unless the data is refreshed on a regular basis. Reducing the power that RAM consumes can make an important contribution to reducing the overall power consumption of portable electronic devices.
RAM devices are generally array structures composed of 2N by 2M individual RAM cells that are coupled to wordlines (rows) and complementary bit lines (columns). A typical RAM memory cell may be composed of between 4 and 6 transistors coupled together to form a data storage device. An individual RAM memory cell may be selected when an X-decoder is used to select rows and a Y-decoder is used to select columns. Typically, data is written into an individual RAM cell when the proper address is selected and WRITE ENABLE circuitry allows digital data in the form of a differential voltage signal to be sent as input to the selected memory cell location. Once a specific memory cell is addressed within a RAM device and a READ ENABLE circuit is active, a very small voltage amplitude representing the addressed digital data is sensed. To produce a readable voltage amplitude representing useful digital data, a sense amplifier is typically implemented to amplify the sensed signal.
FIG. 1 is a block diagram of a conventional RAM wherein digital data is stored within RAM core 100. By way of example, if RAM core 100 is designed with 1,000 rows and 1,000 columns, RAM core 100 may be called a one megabit (1 MB) RAM storage device. In typical architectures, computers access RAM core 100 through an address input bus 110 that may be coupled to a conventional X-DECODER 102 and a conventional Y-DECODER 104. In general, X-DECODER 102 is used for addressing a selected row (wordline) within RAM core 100, and Y-DECODER 104 is used for addressing a selected column (bitlines) within RAM core 100. By way of example, X and Y decoders are generally implemented for reducing memory array aspect ratios by folding (i.e., dividing) long addressable memory columns into several shorter memory columns. Once folded into several columns, the X and Y decoders are capable of reading or writing the addressed data by appropriately performing a suitable multiplexing function.
Once a row and column is selected from RAM core 100, either a write or read operation may be performed on the selected RAM memory cell. In order to perform a write operation, a write control circuit 107 is enabled which allows digital data to be sent as input into a selected RAM memory cell via an input data bus 101. This digital data is in the form of a voltage waveform that represents either a logical “1” or a logical “0”. Input buffer 109 amplifies an input signal 103 that is supplied by RAM input bus 111. The selected transistors in RAM core 100 are then driven to an appropriate state.
Once the row and column is selected in RAM core 100, a read operation may be performed which produces a voltage representing the addressed digital data on a data bus 112. At this point, the addressed digital data may be as low as about 50 millivolts (mV). To read the addressed digital data appropriately, suitable amplification is typically performed in sense amplifier 106. Once the sensed data signal is amplified to full rail voltage level (i.e., in earlier RAM devices, about 5V; in current RAM designs, 3.3V or less) in sense amplifier 106, the voltage amplified data is passed out as amplified data output 114 to an output buffer 108. At output buffer 108, the voltage amplified data 115 is current amplified to provide an appropriate level of current drive once the read data is passed to a RAM output bus 116.
Various techniques have been used to reduce active power consumption in SRAMs and DRAMs of the type illustrated in FIG. 1. These techniques include reducing the RAM operating voltage (Vdd)1 banking the memory cells that comprise the RAM memory and improving and optimizing clock signal distribution within the RAM memory.
Another known method called “virtual ground” has been used to reduce power consumption in RAMs. RAM banks are organized into rows and columns. The number of rows equals the number of words divided by a MUX factor and the number of columns equals the number of bits times the MUX factor. The MUX factor is used to control the aspect ratio of the RAM memory banks. For example, if the MUX factor is 4 and the number of bits equals 16 and the number of words equals 1024, then the number of rows equals 256 and the number of columns equals 64. This means that there are 64 physical memory columns attached to a word line across a row in the RAM memory. When the word line goes high, all 64 RAM core cells attached to that word line activate and begin drawing current. However, in this case only 16 of the 64 columns are required to read or write the correct data. The other 48 columns that are active are wasting power and performing no useful work. A virtual ground eliminates this wasted power. Each individual logic column in the RAM memory bank (words deep) is multiplied into MUXed physical columns and selected by a y-address combination, as shown in FIG. 2. The same y-address that selects which physical column will drive the sense amplifier enables a virtual ground line for that column (the virtual ground line is not illustrated in FIG. 2). All of the virtual grounds for the columns that are not selected are OFF and the columns do not draw current.
Typically, the largest contributor to active power consumption in RAM is writing data to the core memory cells that comprise the RAM. Herein the circuit elements that actually store data written to memory are called core cells. Writing to a RAM core cell usually involves holding one of the core cell's bit lines high (Vdd) and driving the other bit line to ground voltage. The power consumed by writing to the core cell can be defined as:P=CΔV2f, where    P=the total power consumed when writing to the core cell;    C=capacitance of the bit lines and the core cell;    ΔV=the voltage differential between the bit line high and the bit line low; and    f=the clock frequency. Of these, the largest factor is the voltage differential on the bit lines.
One known method to reduce the bit line voltage differential is to use n-channel transistors as pre-charge and equalize devices. As shown in FIG. 3, known core cell 11 has two n-channel transistors 13, coupled respectively to bit line 12 and bit line complement 14. An additional n-channel device 15 is coupled so that its source is coupled to bit line 12 and its drain is coupled to bit line complement 14. The gates of n-channel devices 13 and 15 are all coupled together to a precharge voltage line. When core cell 11 is about to be accessed for writing, this technique charges both bit lines to approximately Vdd−Vtn, where Vtn is the threshold voltage of the n-channel transistors. Typical values for Vtn are from 400 mV to 600 mV. When Vdd was at least approximately 2.5V, this technique was very effective. By equalizing the voltages on the bit lines, the voltage swing needed to write to the cell is reduced, no matter what value is written to the cell. As the needed voltage swing is reduced, the power used to write to the core cell is also reduced.
As process geometries continue to decrease and power supply voltages correspondingly reduce, SRAM core cell noise margins also reduce. This means that a Vdd−Vtn voltage on the bit lines becomes closer to the trip point of the SRAM latch. As the precharge voltage on the bit lines approaches the trip point of the inverters that make up the latch of the core cell, data stability is compromised. In the illustrated core cell of FIG. 3, the access transistors begin to turn on at Vdd−Vtn. As the bit line voltages approach the turn-on voltage of the n-channel access device, this voltage is nearly equal to the precharge voltage when n-channel transistors are used as precharge transistors. With roughly the same voltage on both bit lines as the read cycle begins, the latches that comprise core cell 11 are at nearly their trip point and core cell 11 enters a meta-stable state where the value in the core cell can be corrupted. Under certain circumstances, when accessing a memory cell to read a value from it, a similar voltage imbalance can develop on the differential bit lines. This imbalance can result in the value in the memory cell flipping unpredictably, the resultant value actually written to the core cell potentially being incorrect. As using the precharge circuit of FIG. 3 to reduce power consumption in memory cells no longer produces reliable results, an alternative method must be found to reduce the voltage swing on the bit lines during write operations.